G2992B 台湾致新代理商 GMT LDO系列 DDR终结器
2A DDR Bus Termination Regulator

General Description

The  G2992B  is  a  linear  regulator  designed  to  meet  the  JEDEC  SSTL-18,  SSTL-2  and  SSTL-3  (Series  Stub  Termination Logic) specifications for termination of DDR I/II/  III  -SDRAM.  It  contains  a  high-speed  operational  amplifier  that  provides  excellent  response  to  the  load  transients.  This  device  can  deliver  2A  continuous  cur-rent in the application such as required for DDR I/ II/ III SDRAM  termination.  The  G2992B  can  easily  provide  the  accurate  VTT  voltage  with  two  external  resistors  generating  reference  voltage.  The  quiescent  current  is  as  low  as  750μA  @  VCNTL=  3.3V.  So  the  power  con-sumption can meet the low power consumption applica-tions.  The  G2992B  also  has  a  shutdown  function  by  setting  VREF  smaller  than  0.2V,  that  provides  Suspend  to  RAM  (STR)  functionality.  When  in  the  shutdown  mode, the VTT output (on VOUT pin) will be tri-state pro-viding  a  high  impendence.  A  power  saving  advantage  can  be  obtained  in  this  mode  through  lowering  the  qui-escent current to 50μA @ VCNTL= 3.3V.

Features
„VCNTL Supply Voltage: 3V to 5.5V
„Termination Supply Voltage: 1.2V to 3.6V „
Support DDR I(1.25VTT), DDR II (0.9 VTT), and DDR III(0.75VTT)
Requirements „Requires Only 20μF Ceramic Output Capacitor
„Low Output Offset
„2A Source and Sink Current „
Low External Component Count
„No Inductor Required „
Thermal Shutdown Protection
„Over Current Protection „
Suspend to RAM (STR) Function with High-impedance Output
„SOT-23-5, SOP-8 and MSOP-8 (FD) Package

Applications „
DDR-SDRAM Termination Voltage „
DDR I / DDR II / DDRIII Termination Voltage „
SSTL-18
„SSTL-2 „
SSTL-3

Ordering Information

Note:  T1:  SOT-23-5        
P1:  SOP-8        
F5:  MSOP-8  (FD)            
1:  Bonding  Code  U: Tape & Reel

Pin Configuration

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