|CPU||XBurst®-1 core 600MHZ/1GHZ
– XBurst® RISC instruction set
– XBurst® SIMD128 instruction set
– XBurst® FPU instruction set supporting both single and double floating point format which are IEEE754 compatible
– XBurst® 9-stage pipeline micro-architecture, the operating frequency is 800MHz
|Spirit engine||More than 10 people realtime multi-detection.
Max input resolution 2048x2048 @60fps.
|Video input/output||Video input
– DVP Input data format: YUV422, RGB565, RGB555, RAW8, RAW10, RAW12.
– MIPI CSI2 IN (Ingenic Host Soc Only)
– MIPI CSI2 OUT (Ingenic Host Soc Only)
|Result output||Synchronous serial slave interfaces (SSI_SLV)
– 3 protocols support: Motorola’s SPI, TI’s SSP and National’s Microwire
– Full-duplex, transmit-only or receive-only operation for Motorola’s SPI and TI’s SSP
– Half-duplex, transmit-only or receive-only operation for National’s Microwire
USB 2.0 interface
– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high- /full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions
– 16 Endpoints:
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer